High performance MOS and bipolar analog circuits are necessary for enhancing the performance of very low scale integrated subsystems. For instance, the common-mode rejection, supply rejection, and DC gain of an operational amplifier and other analog circuits are strongly dependent upon the quality of the current sources/transresistance stages that are incorporated in their designs.
Short-channel length MOS devices exhibit a pronounced degradation in output conductance compared with that of long-channel length devices. This becomes even more severe for high speed designs in which the drain current is usually large. The output impedance expression for an MOS device is defined by: EQU r.sub.ds =1/g.sub.ds =1/(.lambda.I.sub.d)=L.sub.eff /{I.sub.d [d(L-L.sub.eff)/dV.sub.ds ]}, (1)
where r.sub.ds is the output impedance, L.sub.eff is the effective channel length, I.sub.d is the drain current, L is the drawn channel length, V.sub.ds is the drain-to-source voltage and g.sub.ds is the drain-to-source conductance. Since small effective channel lengths, L.sub.eff, and large drain currents, I.sub.d, are chosen for fast operations, and short-channel length devices display large values for d(L-L.sub.eff)/dV.sub.ds, therefore the output impedance, r.sub.ds, of an MOS device with a small channel length is significantly smaller than that with large channel length. This can indeed pose a serious problem while designing very high speed and high performance analog circuits.
The degradation of output impedance of MOS devices is prevalent in integrated systems with gate lengths on the order of 2 micron and smaller. In MOS devices with gate lengths as small as 1 micron, many traditional building block circuits fail to function properly because of the low output impedance of the basic transistor.